Date and time: Tuesday 20 October 2026, 12:00-16:00
Where: Digital Futures hub, Osquars Backe 5, floor 2 at KTH main campus
Directions: https://www.digitalfutures.kth.se/contact/how-to-get-here/
Hosted by RISE at Digital Futures
RISC-V, the open standard instruction set architecture, is reshaping how processors are designed, from embedded devices to high-performance computing, and opening new opportunities for European and Swedish semiconductor innovation. This second Swedish RISC-V Meetup brings together industry, academia, startups, and enthusiasts to share results, show hardware, and build collaborations.
The afternoon starts with lunch, followed by an industry talk on real-world RISC-V product and tape-out experience and an academic talk on current research in areas such as custom cores, verification, and security extensions. The panel discussion “From open ISA to Swedish silicon: what would it take to tape out here?” will gather voices from industry and academia, and the day closes with an open floor for collaboration pitches and matchmaking around funding calls (Vinnova, Horizon Europe, Chips JU).
The meetup is open to anyone interested in RISC-V. We are still looking for presenters, so get in touch if you would like a talk, lightning talk, or demo slot.
To participate you need to register. Maximum 50 participants.
Program
12:00 Lunch
13:00 Welcome and recap from RISE
13:15 Industry talk
13:40 Academic talk
14:05 Coffee break and demo corner
14:30 Lightning talks
14:55 Panel: “From open ISA to Swedish silicon—what would it take to tape out here?”
15:35 Open floor: collaboration pitches, funding opportunities, and planning for Meetup #3
Contact
Joakim Eriksson, joakim.eriksson@ri.se
Organisers
Joakim Eriksson, Björn Forsberg, and Tawfik Lazraq, RISE
