Designing high-speed datacenter load balancers
Date and time: 7 December, 15:00 – 16:00 CET
Speaker: Marco Chiesa, KTH Royal Institute of Technology
Title: Designing high-speed datacenter load balancers
Meeting ID: 695 6088 7455
Host/moderator: Tigran Haas, KTH
Abstract: Large service providers use load balancers (LBs) to dispatch millions of incoming connections per second towards thousands of servers. There are two basic yet critical requirements for a load balancer: (i) uniform load distribution of the incoming connections across the servers and (ii) per-connection-consistency (PCC), i.e., the ability to map packets belonging to the same connection to the same server even in the presence of changes in the number of active servers and load balancers. Yet, meeting both these requirements at the same time has been an elusive goal. Today’s load balancers minimize PCC violations at the price of non-uniform load distribution.
In this talk, I will first provide some background on datacenter load balancers and briefly survey the existing work. I will then demonstrate how a slightly more advanced interface between the network and the end hosts dramatically reduces the resources needed to operate load balancers. More specifically, I will show how to move the logic of more than one thousand load balancers into a single high-speed programmable switch, potentially reducing energy consumption by 300x.
Bio: Marco Chiesa is an Assistant Professor at the KTH Royal Institute of Technology, Sweden. He received his PhD degree in computer engineering from Roma Tre University in 2014. His research interests revolve around Internet architectures and protocols, including aspects of network design, optimization, robustness, and privacy. He received the IEEE William R. Bennett Prize in 2020, the IEEE ICNP Best Paper Award in 2013, and the IETF Applied Network Research Prize in 2012. He is currently the PC co-chair for ACM Conext and he has been a distinguished TPC member at IEEE Infocom in 2019 and 2020.